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 scheduling and new classes
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| Author | Topic: scheduling and new classes |
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dennis Member |
posted 11 September 2000 09:32
 
Say that I have a signal-flow diagram containing Sounds A, B, and C. Now I use the ClassEditor to build them into a new class. Will Kyma schedule them differently than if they were not in a class? In particular, will all the Sounds in the new class be scheduled on the same DSP? Sometimes I have to use ForcedProcessorAssignement to get Sounds A, B, and C to share the same physical wavetable, for example. I'm wondering if "binding" them into a new class would clue the compiler to schedule them together. Is there another way? IP: Logged |
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SSC Administrator |
posted 11 September 2000 18:26
The user Sound class is expanded first before it is compiled and scheduled to DSPs, so the scheduling will be the same. Why you need to use ForcedProcessorAssignment Sounds? IP: Logged |
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dennis Member |
posted 12 September 2000 09:31
If I continue with my example (it's simplified from my real case which has more than three sounds), Sounds A, B, and C all reference wavetable 'recording'. Sounds A and B write into 'recording' and C reads from it. If I have a Sound using just A and C, it works fine. If I have a Sound using B and C it works fine too. But when I use A, B, and C altogether, it doesn't work, until I add a ForcedProcessorAssignment at the end of the signal flow and then it works fine too. The DSP Status window shows significant activity on multiple DSPs in the latter case, until I add the ForcedProcessorAssignment. So, without the ForcedProcessorAssignment, I think that I'm getting two 'recording' wavetables in different DSPs and one of the writers (A or B) isn't running on same DSP with the reader (C). Of course, I could be confused about how Kyma schedules Sounds... Is there a better way instead of using ForcedProcessorAssignment? IP: Logged |
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SSC Administrator |
posted 12 September 2000 21:43
The ForcedProcessorAssignment is the way to handle this right now. We have an alpha version of the Sound compiler/scheduler that better handles memory writer/reader combinations. We hope to have a more final version in the next 4-6 weeks. IP: Logged |
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